Computer including installable and removable cards, optical interconnection between cards, and method of assembling a computer

ABSTRACT

A computer comprising a housing; a circuit board supported in the housing; a plurality of slot connectors supported on the circuit board; a first card configured for sliding receipt in one of the slot connectors; a processor mounted on the first card; a second card configured for sliding receipt in one of the slot connectors; a memory mounted on the second card; and an optical interconnect coupling the first card to the second card, the processor being configured to communicate with the memory via the optical interconnect. A method of assembling a computer, the method comprising supporting a circuit board in a housing; supporting a plurality of slot connectors on the circuit board; mounting a processor on a first card; inserting the first card into a first one of the slot connectors; mounting a memory on a second card; inserting the second card into a second one of the slot connectors; and optically coupling the first card to the second card for optical communications between the processor and the memory.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This is a continuation of U.S. patent application Ser. No.10/211,924, which was filed on Aug. 1, 2002, which in turn is acontinuation of U.S. patent application Ser. No. 09/098,050, filed Jun.16, 1998, which is now U.S. Pat. No. 6,453,377, both of which areincorporated by reference herein.

TECHNICAL FIELD

[0002] The invention relates to memory systems. The invention alsorelates to fiber optic systems.

BACKGROUND OF THE INVENTION

[0003] Processor speeds of computers continue to increase. Devices withwhich the processor communicates often do not operate at such highspeeds. For example, static random access memories (SRAMs) often operateat almost as high a speed as the processor, but dynamic random accessmemories (DRAMs) operate at a slower speed. Dynamic random accessmemories possess advantages to static random access memories. Forexample, static random access memories require more space than dynamicrandom access memories.

[0004] Rambus Inc. of Mountain View, Calif. has technology that allowsDRAMs and controllers or processors to transfer data at a highfrequency, such as 600 megabytes per second and above over a RambusChannel, a narrow byte-wide data bus. Attention is directed to thefollowing patents assigned to Rambus Inc., which are incorporated hereinby reference: 5,680,361 to Ware et al.; 5,663,661 to Dillon et al.;5,537,573 to Ware et al.; 5,499,385 to Farmwald et al.; 5,499,355 toKrishnamohan et al.; 5,485,490 to Leung et al.; 5,446,696 to Ware etal.; 5,432,823 to Gasbarro et al.; 5,430,676 to Ware et al.; 5,390,308to Ware et al.; 5,355,391 to Horowitz et al.

[0005] An alternative to Rambus has been developed by memory chipmakers. The synchronous link DRAM (SLDRAM) is an alternative todouble-data-rate (DDR) and Direct Rambus DRAM.

[0006] The SLDRAM is known in the art. The SLDRAM, formerly known asSynchLink, is designed for computer main memory in mobile, desktop,workstation, and server systems. It is designed to reduce a speedbottleneck in accessing memory from a processor. The SLDRAM projectattempts to solve a memory system problem that will become more acute innewer systems. DRAM memory chips do not have enough bandwidth forgetting the data on or off the memory chips. To solve this problem,manufacturers have been using many chips in a wide array to get thespeed up to what their system needs. However, new DRAM chips will haveincreasingly higher capacities, so that there will be so much DRAMcapacity in the wide array of chips needed for getting the speed, thatthe price of the DRAM capacity raises the price of the computer. Forlower price or entry-level computers and workstations, this price may beexcessive. Unnecessarily large memory would exist in baseconfigurations. Although new software uses more memory, that memoryusage is not growing as fast as DRAM density, and this mismatch mayresult in overly expensive computers.

[0007] SLDRAM addresses this problem by using a new architecture forcommunicating with the DRAMs, with two highly optimized buses. Thisallows' increasing the DRAM bandwidth significantly. SLDRAM addspipelined transfer protocol for increased advantage of bandwidth.Attention is directed to the SLDRAM White Paper of 29 Aug. 1997, whichdescribes SLDRAM in greater detail.

[0008] SLDRAMs are synchronously linked to processors. To provide highspeed access to the memories, as processor speed increases, lengths ofcircuit traces should decrease.

[0009] It is known to use optical waveguides as interconnects fromintegrated circuit to integrated circuit. See, for example, U.S. Pat.No. 5,119,451, which is incorporated herein by reference. Various R&Defforts have taken place in an attempt to develop optical interconnecttechnology for short-haul data communications applications such as forcommunications between boards, backplanes, and intra-boxes. See, forexample, “Lighting the Way in Computer Design,” IEEE Circuits & Devices,January 1998.

SUMMARY OF THE INVENTION

[0010] The invention provides a computer. The computer includes ahousing, and a circuit board supported in the housing. A plurality ofslot connectors are supported on the circuit board. A first card isconfigured for sliding receipt in one of the slot connectors. Aprocessor is mounted on the first card. A second card is configured forsliding receipt in one of the slot connectors. A memory is mounted onthe second card. An optical interconnect couples the first card to thesecond card. The processor is configured to communicate with the memoryvia the optical interconnect.

[0011] In one aspect of the invention, the optical interconnectcomprises a fiber optic cable.

[0012] In another aspect of the invention, the optical interconnectcomprises an optical connector on the first card configured to convertbetween electrical signals and optical signals, and the computer furtherincludes circuit traces on the first card coupling the optical connectorto the processor.

[0013] In another aspect of the invention, the optical interconnectcomprises an optical connector on the second card configured to convertbetween electrical signals and optical signals, and the computer furtherincludes circuit traces on the second card coupling the opticalconnector to the memory.

[0014] In another aspect of the invention, the memory comprises a DRAM.In another aspect of the invention, the memory comprises a synchronouslink type DRAM.

[0015] Another aspect of the invention provides a memory unit configuredto be slidably received in a slot connector on a circuit board. Thememory unit comprises a card having a connector configured to mate withthe slot connector. A synchronous link DRAM memory is supported by thecard. Circuit traces on the card extend from the connector of the cardtoward the memory. The circuit traces are configured to couple thememory to a power supply via the slot connector. An optical interface issupported by the card and coupled to the memory. The optical interfaceis configured to convert electrical signal to optical signals, foroptical data transmission to and from the memory.

[0016] Another aspect of the invention provides a method of assembling acomputer. The method comprises supporting a circuit board in a housing.A plurality of slot connectors are supported on the circuit board. Aprocessor is mounted on a first card. The first card is inserted into afirst one of the slot connectors. A memory is mounted on a second card.The second card is inserted into a second one of the slot connectors.The first card is optically connected to the second card for opticalcommunications between the processor and the memory.

[0017] By reducing the circuit trace path on a memory card,communication speed is increased. Inexpensive circuit cards can be usedinstead of Teflon substrate or low dielectric cards. Memory integratedcircuits can be mounted on cards prior to burn-in because the circuitcards are inexpensive. This is less expensive than burning-in memoryintegrated circuits before they are mounted on circuit cards.Unsophisticated users can add memory and integrated circuits easily.They can insert a SIMM module or card, attach one end of the fiber opticcable to an optical interconnect on the SIMM module, and attach theother end of the fiber optic cable to the optical interface on theprocessor card, and the installation is complete. Electromagneticinterference caused by power supply transformers or disk drives is lessof a concern because the optical communications are immune to suchinterference.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0019]FIG. 1 is a perspective view of a computer embodying theinvention.

[0020]FIG. 2 is a perspective view of a computer, illustrating removalof a card bearing a processor.

[0021]FIG. 3 is a perspective view of a computer, illustrating insertionof a card bearing a processor.

[0022]FIG. 4 is a perspective view of a computer, illustrating a cardbearing a processor in accordance with an alternative embodiment of theinvention.

[0023]FIG. 5 is a perspective view of a computer in accordance with analternative embodiment of the invention.

[0024]FIG. 6 is a perspective view of a computer in accordance withanother alternative embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0026]FIG. 1 illustrates a computer 10 embodying the invention. Thecomputer comprises a housing 12, and a circuit board 14 supported in thehousing 12. The computer 10 further includes a plurality of slotconnectors 16, 18, 20, 22 supported on the circuit board, and a firstcard 24 configured for sliding receipt in one of the slot connectors(e.g., the slot connector 16).

[0027] The first card 24 has an edge connector 26 configured for slidingreceipt in the slot connector 16. The computer 10 further includes aprocessor 28 mounted on the first card 24.

[0028] The computer 10 further includes a second card 30 configured forsliding receipt in one of the slot connectors (e.g., the slot connector18). The second card 30 has an edge connector 32 configured for slidingreceipt in the slot connector 18.

[0029] Because the processor 28 is mounted on a removable card, it canbe more easily upgraded. Instead of having to insert a processor 28 in asocket after aligning pins, the card 24 can be removed (FIG. 2) andreplaced (FIG. 3) with a new card 34 bearing a new processor 36. Thus,in one embodiment (FIGS. 1-3), the processor 28 is surface mounted onthe card 24. However, in an alternative embodiment (FIG. 4), the secondcard 30 includes a zero insertion force (ZIF) connector or socket 38 orother socket, and the processor 28 is removable received in the socket38.

[0030] The computer 10 further includes a memory 40 mounted on thesecond card 30 (FIG. 2). In the illustrated embodiment, the memory 40comprises a DRAM. In a more particular embodiment, the memory 40comprises a synchronous link type DRAM. In the illustrated embodiment,the memory 40 is defined by one or more integrated circuits. In oneembodiment, the computer 10 further comprises additional integratedcircuits 42 supported by the second card 30. These can be additionalmemory integrated circuits, for example.

[0031] The computer 10 further includes an optical interconnect 44coupling the first card 24 to the second card 30. The processor 28 isconfigured to communicate with the memory 40 via the opticalinterconnect 44. The optical interconnect 44 thus couples the processor28 to the memory 40 for data communications. In the illustratedembodiment, the computer 10 includes a 32 bit communications bus and theoptical interconnect has capacity for a multiple of the bus width pluscontrol signals indicating whether data is to be sent or transmission iscomplete.

[0032] The optical interconnect 44 comprises a fiber optic cable (or setof fiber optic cables) 46 having opposite ends 52 and 54. The opticalinterconnect 44 further comprises an optical connector on the first card24 configured to convert between electrical signals and optical signals,and an optical connector on the second card 30 configured to convertbetween electrical signals and optical signals. Any suitable opticalconnectors can be employed, such as those described in the articleslisted above in the Background of the Invention. For example, in oneembodiment, the optical connectors and include a VCSEL opticaltransmitter array 48 and a VCSEL optical receiver array 50 on each card24 and 30. The optical connectors 48 and 50 on the first and secondcards 24 and 30 removably receive ends 52 and 54 of the fiber opticcable (or set of fiber optic cables) 46 directly or via a connector 94.In one embodiment, the ends of the cables from the cards 30 and 66 haveseparate connectors that respectively connect to the connector 50. Inone embodiment, the cable 46 is a Polyguide™ waveguide available fromE.I. du Pont de Nemours & Co., Inc., or a waveguide developed under thePOINT program. In the illustrated embodiment, the optical connectors 48and 50 connect or mate to an end 52 or 54 of a fiber optic cable 46 byhand, without need for a tool.

[0033] In one embodiment, shown in FIG. 5, only a single fiber opticcable or set 90 of fiber optic cables extends from the card 30. Thesingle set is used for both transmission and reception of data. The sethas a number of cables for reception that is equal to or a multiple ofthe bus width of the computer. The set also has a number of cables fortransmission that is equal to or a multiple of the bus width of thecomputer. The set also has cables for control signals used to indicatedata is about to be sent or that data transmission is complete. In theillustrated embodiment, the bus width is 32 bits.

[0034] Similarly, in the embodiment of FIG. 5, only a single fiber opticcable or set 92 extends from the card 66.

[0035] The computer 10 further includes circuit traces 56 on the firstcard 24 coupling the optical connector 48 to the processor 28 (FIG. 2).The computer 10 further includes circuit traces 58 on the second card 30coupling the optical connector 50 to the memory 40 (and memories 42).The computer 10 further including multiple respective circuit traces 59coupling the integrated circuits 40 and 42 supported by the second card30 to the edge connector 32 of the second card 30. Because the edgeconnector 32 is not used for data communication, additional traces atthe edge connector can be used for power. More particularly, respectiveintegrated circuits 40, 42 can have their own traces extending directlyto the edge connector 32 instead of being coupled together on the secondcard 30.

[0036] The computer 10 further includes a power supply 60 in the housing12 (FIG. 1), and conductors coupling the power supply 60 to theprocessor 28 via the slot connector. The conductors include circuittraces 62 on the first card 24 extending from the edge connector 26 ofthe first card to the processor 28. Additional circuit traces (notshown) can be used to supply power to the optical connectors. Thecomputer 10 further includes conductors coupling the power supply 60 tothe memory 40 via the slot connector 18. The conductors include thecircuit traces 59 extending from the edge connector 32 of the secondcard 30 to the memory 40.

[0037] The slot connectors 16, 18, 20, and 22 and edge connectors 26 and32 are used for supplying power to the processor 28 and memory 40 andperhaps for control functions, but not for data communication betweenthe processor 28 and the memory 40.

[0038] In one embodiment, the computer 10 further includes a third card66 having an edge connector 68 configured for sliding receipt in theslot connector 22. The computer 10 further includes a co-processor 70supported by the third card 66, and an optical interconnect 72 couplingthe co-processor 70 to the processor 28. The computer 10 furtherincludes conductors coupling the power supply to the co-processor viathe slot connector 20. The conductors include circuit traces 74 on thethird card 66 extending from the edge connector 68 of the third card 66to the co-processor 70. In the illustrated embodiment, the co-processor70 is a math co-processor. In one embodiment, the third card 66 supportsa Motherboard Control and Interface Chipset such as a Trident™ chipset.

[0039] The computer 10 further includes an electronic device in thehousing capable of generating electromagnetic interference. For example,the power supply 60 includes a transformer capable of generatingelectromagnetic interference. The computer 10 further includes a floppydisk drive 76, a hard drive 78, and a CD-ROM drive 80 coupled to theboard 14. The optical interconnect 44 shields communications between theprocessor 28 and the memory 40 from the electromagnetic interference.The computer 10 can further include any component typically found incomputers.

[0040] A monitor 82 and input/output devices (printer, keyboard, mouse)84 can be removably coupled to the computer 10 in a conventional fashion(e.g., via parallel and serial ports included in the computer).

[0041] Another alternative embodiment is shown in FIG. 6. The embodimentof FIG. 6 is similar to the embodiment of FIG. 4, like referencenumerals indicating like components, except that the processor 28 ismounted to the main circuit board (motherboard) 14 instead of beingmounted on a removable card. In the illustrated embodiment, theprocessor is mounted on the motherboard 14 via a ZIF socket 38. In analternative embodiment, the processor 28 is hard wired onto themotherboard 14. In these embodiments, co-processors and similar chipsetmay also be mounted on the motherboard 14 instead of being mounted on aremovable card.

[0042] A computer such as the computer 10 can be assembled as follows.The circuit board 14 is supported in the housing 12. The plurality ofslot connectors 16, 18, 20, and 22 are supported on the circuit board(either before or after the circuit board 14 is supported in the housing12). The processor 28 is mounted on the first card 24. The first card 24is mounted into the slot connector 16. The memory 40 is mounted on thesecond card 30. The second card 30 is inserted into the slot connector18. The first card 24 is optically coupled to the second card 30 foroptical communications between the processor 28 and the memory 40.

[0043] By reducing the circuit trace path on a memory card,communication speed is increased. Inexpensive circuit cards can be usedinstead of Teflon substrate or low dielectric cards. Memory integratedcircuits can be mounted on cards prior to burn-in because the circuitcards are inexpensive. This is less expensive than burning-in memoryintegrated circuits before they are mounted on circuit cards.Unsophisticated users can add memory and integrated circuits easily.They can insert a memory module or card, attach one end of the fiberoptic cable to an optical interconnect on the memory card, and attachthe other end of the fiber optic cable to the optical interface on theprocessor card, and the installation is complete. Electromagneticinterference caused by power supply transformers or disk drives is lessof a concern because the optical communications are immune to suchinterference.

[0044] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

The invention claimed is:
 1. A system comprising: a housing; a circuitboard supported in the housing; a plurality of slot connectors supportedon the circuit board; a first card in one of the slot connectors; afirst circuit component mounted on the first card; a second card inanother one of the slot connectors; a second circuit component mountedon the second card; and an optical interconnect coupling the first cardto the second card, the first circuit component being configured tocommunicate with the second circuit component via the opticalinterconnect, whereby the optical interconnect does not pass through theslot connectors so that interference that could otherwise be caused bysignals to and from the first circuit component is impeded.
 2. A systemin accordance with claim 1 wherein the optical interconnect comprises afiber optic cable.
 3. A system in accordance with claim 1 wherein theoptical interconnect comprises an optical connector on the first cardconfigured to convert between electrical signals and optical signals,and wherein the computer further includes circuit traces on the firstcard coupling the optical connector to the first circuit component.
 4. Asystem in accordance with claim 1 wherein the optical interconnectcomprises an optical connector on the second card configured to convertbetween electrical signals and optical signals, and wherein the computerfurther includes circuit traces on the second card coupling the opticalconnector to the second circuit component.
 5. A system in accordancewith claim 1 wherein the optical interconnect comprises a first opticalconnector, on the first card, configured to convert between electricalsignals and optical signals, wherein the computer further includescircuit traces on the first card coupling the first optical connector tothe first circuit component, wherein the optical interconnect furthercomprises an optical connector, on the second card, configured toconvert between electrical signals and optical signals, the computerfurther including circuit traces on the second card coupling the secondoptical connector to the second circuit component.
 6. A system inaccordance with claim 1 wherein the second circuit component comprises aDRAM.
 7. A system in accordance with claim 1 wherein the second circuitcomponent comprises a synchronous link type DRAM.
 8. A systemcomprising: a housing; a circuit board supported in the housing; a slotconnector supported on the circuit board; a first circuit componentsupported by the circuit board; a card removably received in one of theslot connectors; a second circuit component mounted on the card; and anoptical interconnect coupling the card to the circuit board, the firstcircuit component being configured to communicate with the secondcircuit component via the optical interconnect, whereby the opticalinterconnect does not pass through the slot connectors so thatinterference that could otherwise be caused by signals to and from thefirst circuit component is impeded.
 9. A system in accordance with claim8 wherein the first circuit component is hard wired to the circuitboard.
 10. A system in accordance with claim 8 and further comprising aZIF connector mounted to the circuit board, and wherein the firstcircuit component is removably received in the ZIF connector.
 11. Asystem in accordance with claim 8 wherein the optical interconnectcomprises an optical connector on the card configured to convert betweenelectrical signals and optical signals, and an optical connector on thecircuit board configured to convert between electrical signals andoptical signals.
 12. A system in accordance with claim 8 wherein thefirst circuit component comprises a DRAM.
 13. A system in accordancewith claim 8 wherein the first circuit component comprises a synchronouslink type DRAM.
 14. A computer comprising: a housing; a circuit boardsupported in the housing; a plurality of connectors supported on thecircuit board; a first card in a first one of the connectors; aprocessor supported by the first card; a second card in a second one ofthe connectors; a synchronous link DRAM memory supported by the secondcard; a power supply in the housing; conductors coupling the powersupply to the processor via the first connector, the conductorsincluding circuit traces on the first card; conductors coupling thepower supply to the memory via the second connector, the conductorsincluding circuit traces on the second card; and an optical interconnectcoupling the processor to the memory for data communications, theoptical interconnect being within the housing, in use, wherein theoptical interconnect does not pass through the connectors.
 15. Acomputer in accordance with claim 14 and further comprising a third cardin a third one of the connectors, a co-processor supported by the thirdcard, and an optical interconnect coupling the co-processor to theprocessor.
 16. A computer in accordance with claim 15 and furthercomprising conductors coupling the power supply to the co-processor viathe third connector, the conductors including circuit traces on thethird card.
 17. A computer in accordance with claim 15 wherein theco-processor is a math co-processor.
 18. A computer in accordance withclaim 15 and further including an electronic device in the housingcapable of generating electromagnetic interference, and wherein theoptical interconnect shields communications between the processor andthe memory from the electromagnetic interference.
 19. A computercomprising: a housing; a circuit board supported in the housing; aplurality of connectors supported on the circuit board; a first card ina first one of the connectors; a first integrated circuit supported bythe first card; a second card in a second one of the connectors; asecond integrated circuit supported by the second card; a power supplyin the housing; conductors coupling the power supply to the firstintegrated circuit via the first connector, the conductors includingcircuit traces on the first card; conductors coupling the power supplyto the second integrated circuit via the second connector, theconductors including circuit traces on the second card; and an opticalinterconnect coupling the first integrated circuit to the secondintegrated circuit for data communications, the optical interconnectbeing within the housing, in use, wherein the optical interconnect doesnot pass through the connectors.
 20. A computer in accordance with claim19, and further comprising a third card in a third one of theconnectors, a co-processor supported by the third card, and an opticalinterconnect coupling the co-processor to the processor wherein thefirst integrated circuit comprises a processor, and wherein the secondintegrated circuit comprises a memory.
 21. A computer in accordance withclaim 20 and further comprising conductors coupling the power supply tothe co-processor via the third connector, the conductors includingcircuit traces on the third card.
 22. A computer in accordance withclaim 20 wherein the co-processor is a math co-processor.
 23. A computerin accordance with claim 20 and further including an electronic devicein the housing capable of generating electromagnetic interference, andwherein the optical interconnect shields communications between theprocessor and the memory from the electromagnetic interference.
 24. Amethod of assembling a system, the method comprising: supporting acircuit board in a housing; supporting a plurality of slot connectors onthe circuit board; mounting a first circuit component on a first card;inserting the first card into a first one of the slot connectors;mounting a second circuit component on a second card; inserting thesecond card into a second one of the slot connectors; and flexiblyoptically coupling the first card to the second card for opticalcommunications between the first circuit component and the secondcircuit component, whereby the flexible optical interconnect does notpass through the slot connectors so that interference that couldotherwise be caused by signals to and from the first circuit componentis impeded.
 25. A method of assembling a system in accordance with claim24 wherein optically coupling the first card to the second cardcomprises using a fiber optic cable.
 26. A method of assembling a systemin accordance with claim 24 wherein optically coupling the first card tothe second card comprises supporting an optical connector on the firstcard to convert between electrical signals and optical signals, andforming circuit traces on the first card to couple the optical connectorto the first circuit component.
 27. A method of assembling a system inaccordance with claim 24 wherein optically coupling the first card tothe second card comprises supporting an optical connector on the secondcard to convert between electrical signals and optical signals, andforming circuit traces on the second card to couple the opticalconnector to the second circuit component.
 28. A method of assembling asystem in accordance with claim 24 wherein optically coupling the firstcard to the second card comprises supporting an optical connector on thefirst card to convert between electrical signals and optical signals,forming circuit traces on the first card to couple the optical connectorto the first circuit component, supporting an optical connector on thesecond card to convert between electrical signals and optical signals,and forming circuit traces on the second card to couple the opticalconnector to the second circuit component.
 29. A method of assembling asystem in accordance with claim 24 wherein mounting the second circuitcomponent comprises mounting a DRAM on the first card.
 30. A method ofassembling a system in accordance with claim 24 wherein mounting thesecond circuit component comprises mounting a synchronous link type DRAMon the first card.
 31. A method comprising: supporting a circuit boardin a housing; supporting a plurality of slot connectors on the circuitboard; supporting a processor on a first card having an edge connector;inserting the edge connector of the first card into a first one of theslot connectors to support the first card from the circuit board;providing a second card having an edge connector configured for slidingreceipt in a second one of the slot connectors; supporting a synchronouslink DRAM memory on a second card having an edge connector; insertingthe edge connector of the second card into a second one of the slotconnectors to support the second card from the circuit board; supportinga power supply in the housing; coupling the power supply to theprocessor via the first slot connector, the coupling including usingcircuit traces on the first card extending from the edge connector ofthe first card toward the processor; coupling the power supply to thememory via the second slot connector, the coupling including usingcircuit traces on the second card extending from the edge connector ofthe second card toward the memory; and optically coupling the processorto the memory for data communications using an optical interconnectwithin the housing, wherein the optical interconnect does not passthrough the slot connectors.
 32. A method in accordance with claim 31and further comprising supporting a co-processor on a third card havingan edge connector, and optically coupling the co-processor to theprocessor.
 33. A method in accordance with claim 32 and furthercomprising coupling the power supply to the co-processor via the thirdslot connector, the coupling comprising using circuit traces on thethird card extending from the edge connector of the third card towardthe co-processor.
 34. A method in accordance with claim 32 whereinsupporting a co-processor comprises supporting a math co-processor onthe third card.
 35. A method comprising: supporting a circuit board in ahousing; supporting a plurality of slot connectors on the circuit board;supporting a first integrated circuit on a first card having an edgeconnector; inserting the edge connector of the first card into a firstone of the slot connectors to support the first card from the circuitboard; providing a second card having an edge connector configured forsliding receipt in a second one of the slot connectors; supporting asecond integrated circuit on a second card having an edge connector;inserting the edge connector of the second card into a second one of theslot connectors to support the second card from the circuit board;supporting a power supply in the housing; coupling the power supply tothe first integrated circuit via the first slot connector, the couplingincluding using circuit traces on the first card extending from the edgeconnector of the first card toward the first integrated circuit;coupling the power supply to the second integrated circuit via thesecond slot connector, the coupling including using circuit traces onthe second card extending from the edge connector of the second cardtoward the second integrated circuit; and optically coupling the firstintegrated circuit to the second integrated circuit for datacommunications using an optical interconnect within the housing, whereinthe optical interconnect does not pass through the slot connectors. 36.A method in accordance with claim 35 and further comprising supporting aco-processor on a third card having an edge connector, and opticallycoupling the co-processor to the processor, wherein the first integratedcircuit comprises a processor, and wherein the second integrated circuitcomprises a memory.
 37. A method in accordance with claim 36 and furthercomprising coupling the power supply to the co-processor via the thirdslot connector, the coupling comprising using circuit traces on thethird card extending from the edge connector of the third card towardthe co-processor.
 38. A method in accordance with claim 36 whereinsupporting a co-processor comprises supporting a math co-processor onthe third card.
 39. A system comprising: a housing; a circuit boardsupported in the housing; a plurality of slot connectors supported onthe circuit board; a first card configured for sliding receipt in one ofthe slot connectors; a first circuit component mounted on the firstcard; a second card configured for sliding receipt in one of the slotconnectors; a second circuit component mounted on the second card; andan optical interconnect coupling the first card to the second card, thefirst circuit component being configured to communicate with the secondcircuit component via the optical interconnect, whereby the opticalinterconnect does not pass through the slot connectors so thatinterference that could otherwise be caused by signals to and from thefirst circuit component is impeded.
 40. A system in accordance withclaim 39 wherein the optical interconnect comprises a fiber optic cable.